Find the FSV (full scale voltage) in a 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V.
Answer: A
No Explanation.
Enter details here
In a shift left register, shifting a bit by one bit means
Answer: B
In binary shift one bit left means multiplication by 2.
Enter details here
Assertion (A): Synchronous counter has higher speed of operation than ripple counter
Reason (R): Synchronous counter uses high speed flip flops.
Answer: C
Higher speed is due-to the reason that clock pulses in synchronous counter are applied simultaneously to all the flip-flops.
Enter details here
The number of cells in a 4 variable K map is
Answer: A
No Explanation.
Enter details here
A DAC has full scale output of 5 V. If accuracy is ± 0.2% the maximum error for an output of 1 V is
Answer: B
No Explanation.
Enter details here
What will be conversion time of a successive approximation A/D converter which uses 2 MHz clock and 5 bit binary ladder containing 8 V reference.?
Answer: A
No Explanation.
Enter details here
In a BCD to 7 segment decoder the minimum and maximum number of outputs active at any time is
Answer: A
Minimum number of outputs when input is decimal 1 and maximum number of outputs when input is decimal 8.
Enter details here
A 4 bit ripple counter starts in 0000 state. When the counter reads 0010 the number of clock pulses which have occurred is
Answer: D
At pulse 1 the state changes to 0001 and at pulse 2 it changes to 0010 Since it has a total of 16 states, the counter returns to 0000 after 16 and 32 pulses.
Enter details here
Which of the following is non-saturating?
Answer: C
Since it is non-saturating, ECL has low propagation delay.
Enter details here
A 16:1 multiplexer has 4 select input lines.
Answer: A
No Explanation.
Enter details here